Network switch circuits are commonly used to transfer information packets among two or more busses. The network switch accommodates busses operating at different rates, using different protocol and having different latency specifications. The information packets contain headers and trailers that are unique to a particular bus that should be added, altered or deleted when transferred to another bus.
Referring to FIG. 1, a block diagram of a simplified conventional two port store-and-forward Ethernet switch 10 is shown. Each input to switch ports 12 and 14 writes Ethernet packets to locations in a packet buffer memory 16. Outputs from the switch ports 12 and 14 read packets from locations in the packet buffer memory 16. Locations of the packets in the packet buffer memory 16 are dynamically allocated by a buffer memory manager 18 when new packets arrive and then deallocated when the packets leaves a switch port 12 or 14. The buffer memory manager 18 can be a simple stack of memory pointers. The switch ports 12 and 14 read pointers from the stack upon receipt of an input packet and return pointers to the stack upon transmitting an output packet.
Referring to FIG. 2, a block diagram of a conventional communication switch device 20 is shown. The device 20 includes several ports 22, 24, 26 and 28 sharing a central memory 30. The central or bulk memory 30 is typically a synchronous dynamic random access Memory (SDRAM). Each port 22, 24, 26 and 28 commonly has a different memory utilization. For example, an asynchronous transfer mode (ATM) modem connected to the device 20 often works with very small cells (i.e., 48 bytes) and with very large packets (i.e., 64 k bytes). ATM packets may be very heavily interleaved, one at a time, and thus the device 20 many store a number of partially received packets. However, a router/firewall (not shown) often adds or strips headers from the ATM packets. The router/firewall changes the size, and the starting address of the ATM packets. The Ethernet switch port 22 may “broadcast” a packet by sending packets to several ports simultaneously. Therefore, the device 20 stores multiple copies of the broadcast Ethernet packets. The voice processor port 26 commonly has a low latency specification. Thus, voice packets are moved through the bulk memory 30 rapidly. Furthermore, the virtual private network (VPN) processor port 28 and the digital subscriber line (DSL) Wide Area Network (WAN) port 24 uses the device resources differently than the Ethernet switch port 22 or the voice processor port 26.
Several methods exist for controlling the device 20 in simple communication systems. For example, linked-list data structures can be provided by a central processor unit (CPU) 32 and stored in an external memory 34. The ports 22, 24, 26 and 28 then read/write data to linked lists of buffers stored in the bulk memory 30. The CPU 32 adjusts the linked-list pointers and allocates/deallocates blocks of the bulk memory 30.
Control problems can arise for complex communication system for several reasons. For example, a large amount of processing power for the CPU 32 is utilized to maintain the linked lists and to allocate the bulk memory 30. Because the linked lists are usually in the external (i.e., high latency) memory 34, the CPU 32 often waits for memory accesses. In addition, maintaining the linked lists in the external memory 34 consumes a lot of memory bandwidth. For small packets, maintaining the linked list can use more memory bandwidth than the data. Furthermore, the CPU 32 utilizes processing resources to manage “broadcast” packets.
Another conventional control solution is to use an on-chip stack of pointers (not shown). The on-chip pointer stack avoids problems with external memory bandwidth and latency. Furthermore, the pointer stack solution does not burden the CPU 32 and keeps an internal copy-count for broadcast packets. However, the on-chip stack does not support linking small buffers to create larger buffers. Thus inefficient memory usage results for ports such as the DSL WAN port 24 where there are widely varying packet sizes. In addition, the on-chip stack is integrated into the device 20. No clear mechanism is present for other devices to share the stack. Also, the pointer stack does not provide a straightforward mechanism for the device 20 to add/strip header information.
Memory leaks are also a common problem with conventional dynamic memory allocation systems. Memory leaks occur when a buffer is allocated but never deallocated. For complex systems, with several devices, memory leaks are very difficult to debug and correct.